1. Field of the Invention
The present invention relates to a method for forming an electrically-erasable programmable read-only-memory (EEPROM) cell and, more particularly, to a method for reducing the capacitance across the layer of tunnel oxide of the cell.
2. Description of the Related Art
An electrically-erasable programmable read-only-memory (EEPROM) cell is an information storage device that utilizes the non-volatile storage of an electric charge as the information storage mechanism. EEPROM cells differ from other non-volatile memory cells in that EEPROM cells are both programmed and erased by means of Fowler-Nordheim tunneling.
FIG. 1 shows a cross-sectional diagram that illustrates a portion of a conventional EEPROM cell 10. As shown in FIG. 1, EEPROM cell 10 includes buried N+ (BN+) source and drain regions 14 and 16, respectively, which are formed in a lightly-doped p-type substrate 12, and BN+ oxide regions 18 and 20 which are grown over BN+ source and drain regions 14 and 16, respectively. BN+ oxide region 20, in turn, includes a tunnel window 22 that exposes a portion of drain region 16.
As further shown in FIG. 1, EEPROM cell 10 also includes a thin layer of tunnel oxide 24 that is formed over drain region 16 in tunnel window 22, and a thicker layer of gate oxide 26 that is formed over substrate 12 between BN+ source and drain regions 14 and 16. In addition, EEPROM cell 10 further includes a floating gate 30 which is formed over BN+ oxide regions 18 and 20, tunnel oxide layer 24, and gate oxide layer 26, and a control gate 34 which is formed over floating gate 30 and isolated therefrom by a layer of interpoly dielectric 32.
In operation, cell 10 is programmed by applying a program voltage to control gate 34, grounding BN+ drain region 16, and floating BN+ source region 14. Under these bias conditions, electrons from drain region 16 tunnel through tunnel oxide layer 24 by way of the well-known Fowler-Nordheim tunneling mechanism, and begin accumulating on floating gate 30 where the increased negative charge raises the threshold voltage of the cell.
Similarly, cell 10 is erased by grounding control gate 34, applying an erase voltage to BN+ drain region 16, and floating BN+ source region 14. Under these bias conditions, electrons from floating gate 30 tunnel back through tunnel oxide layer 24 to drain region 16 where the reduced negative charge on floating gate 30 lowers the threshold voltage of the cell. (The thickness of gate oxide layer 26 and the magnitudes of the program and erase voltages are selected so that Fowler-Nordheim tunneling does not occur through gate oxide layer 26).
Once programmed or erased, cell 10 is read by applying a first read voltage to control gate 34, grounding source region 14, and applying a second read voltage to drain region 16. When cell 10 is erased, a large current will flow from drain region 16 to source region 14 due to the lower threshold voltage of an erased cell, while a much smaller current or no current at all will flow from drain region 16 to source region 14 when cell 10 is programmed due to the higher threshold voltage of a programmed cell.
One of the limitations of EEPROM cell 10 is that, during the fabrication of cell 10, a wet etch process is conventionally used to form tunnel window 22 in BN+ oxide region 20 due to the need to preserve the integrity of the silicon at the surface of drain region 16. By preserving the integrity of the silicon, a higher quality layer of tunnel oxide can be grown over the surface of drain region 16 than can be grown following the use of a standard dry etch process.
The drawback of using a conventional wet etch process, however, is that the process is isotropic. As a result, the size of the tunnel window produced by a conventional wet etch process is significantly larger than the size of the tunnel window produced by a standard dry etch process.
The drawback of a large tunnel window is that as the size of the tunnel window increases, the capacitance across the layer of tunnel oxide increases which, in turn, decreases the threshold voltage range of the cell. A decreased threshold voltage range, in turn, produces a number of undesirable results that include a reduced manufacturing yield, an increased time to read the cell, and a shortened endurance life of the cell.
FIG. 2 shows a graphical diagram that illustrates these undesirable results by comparing the programming window of a cell with a large tunnel window to the programming window of a cell with a small tunnel window. As shown in FIG. 2, when a cell is programmed with a predetermined program voltage for a predetermined period of time, the cell having a small tunnel window is programmed to a threshold voltage V.sub.PS while the cell having a large tunnel window is programmed to a threshold voltage V.sub.PL.
The difference in the programmed threshold voltages V.sub.P is caused by the increased capacitance across the layer of tunnel oxide that is associated with a larger tunnel window. The increased capacitance reduces the program/erase voltage across the layer of tunnel oxide which, in turn, reduces the number of electrons that can tunnel through the layer of tunnel oxide for a specified program/erase time (typically 5-10 mS). By reducing the number of tunneling electrons, the programmed threshold voltage of the cell is also reduced.
Similarly, when the cell is erased with a predetermined erase voltage for a predetermined period of time, the cell having a small tunnel window is erased to a threshold voltage V.sub.ES while the cell having a large tunnel window is erased to a threshold voltage V.sub.EL. The difference between the programmed and erased threshold voltages V.sub.P and V.sub.E, in turn, defines the programming window of the cell. Thus, as shown in FIG. 2, the threshold voltage range, or the programming window, of a cell with a large tunnel window is less than the threshold voltage range of a cell with a smaller tunnel window.
Although FIG. 2 shows both of the programming windows with fixed threshold voltages V.sub.PS /V.sub.PL and V.sub.ES /V.sub.EL, the actual threshold voltages of a given sample of EEPROM cells are distributed around the programmed and erased threshold voltages V.sub.PS /V.sub.PL and V.sub.ES /V.sub.EL.
As a result, some number of EEFPROM cells from a given sample will have a programmed threshold voltage V.sub.P that is so low that the cell is read as erased when the cell is actually programmed, while some number of EEPROM cells will have an erased threshold voltage V.sub.E that is so high that the cell is read as programmed when the cell is actually erased.
Thus, since cells with a large tunnel window and, therefore, a large capacitance across the layer of tunnel oxide, have an overall distribution of programmed and erased threshold voltages that are lower and higher, respectively, than the overall distribution of cells with a smaller tunnel window and a smaller capacitance, there will be more large tunnel window cells that produce an erroneous reading than small tunnel window cells, thereby reducing the manufacturing yield.
In addition, conventional EEPROM cells are read by comparing the current that flows through a cell with a reference current. The time required to make the comparison is a function of the difference in the magnitudes of the two currents, with a large difference in magnitude between the cell current and the reference current requiring less time than a small difference in magnitude.
Thus, for example, when an erased cell is read, the cell current should be much greater than the reference current to read the cell in the shortest amount of time. However, since cells with a large tunnel window and, therefore, a large capacitance, have an overall distribution of erased threshold voltages V.sub.E that is higher than the overall distribution of cells with a smaller tunnel window and a smaller capacitance, cells with a large tunnel window will output less current when read than cells with a smaller tunnel window. The reduced current flow reduces the difference in magnitude between the cell current and the reference current which, in turn, increases the time required to read the cell.
Further, repeated programming and erasing over the lifetime of a cell cause traps to be formed in the tunnel oxide which, in turn, gradually reduce the programmed threshold voltages V.sub.P of the cells, and gradually increase the erased threshold voltages V.sub.E. As a result, this process, known as window narrowing, continually reduces the programming window of the cells and eventually causes the cells to fail.
Thus, since cells with a large tunnel window and capacitance have an overall distribution of programmed threshold voltages that is lower than the overall distribution of cells with a smaller tunnel window and capacitance, cells with a large tunnel area will suffer from reduced program/erase margins and fail sooner than cells with a smaller tunnel window.
Therefore, in view of the above, there is a need for a method for reducing the capacitance across the layer of tunnel oxide in an EEPROM cell.